X3D and the same increased L3 cache are a pointless crutch on x86 due to the shamefully low RAM bandwidth on all x86 in the consumer segment, but not on servers, where the bandwidth has long exceeded 1TB/s with HBM3+ memory.
It will be interesting to see when the delayed Zen5 Strix Halo with a 256-bit controller finally comes out - what will be the efficiency of the memory controller. I bet that it will hardly be more than 60% there. Apple, to its shame, even in top SoCs with a 512-bit controller actually provided only 30-33% of the theoretical declared bandwidth of 400 GB/s. Hence their epic failure with igpu - the lack of bandwidth for shared system memory is obvious.
At the prices that Apple demands for laptops with Max chips, they could very well install soldered 16-32GB of HBM3 memory directly in the chiplet as independent VRAM, like AMD in their SoCs, but something holds them back even in the HEDT segment from an obvious solution that will speed up igpu several times and provide easy support for many of the latest standards like DP2.0+/UHBR20 for 8k monitors, which we have been sadly waiting for at least 11 years in the mass segment...