AMD Strix Halo die size and TDP configurations revealed by new leak

[Redaktion]

A new leak has revealed some interesting information about AMD's upcoming Strix Halo laptop chips. It will come with 2 Zen 5 CCDs, an RDNA 5 GPU and LPDDR5x 8,533 RAM.

https://www.notebookcheck.net/AMD-Strix-Halo-die-size-and-TDP-configurations-revealed-by-new-leak.870438.0.html

[NikoB (old nm bl)]

It also says Strix Halo will come with LPDDR5x 8,533 RAM on a 256-bit bus for a total memory bandwidth of about 270 GB/s and confirms the platform can be configured with up to 128 GB of RAM.

This is just a theoretical calculation that has nothing to do with the real efficiency of the memory controller, as real tests of Apple chip memory controllers have shown us, their efficiency is simply shameful, despite the bravura declarations about the wonderful 400 GB / s with a 512-bit memory bus.

Accordingly, rumors about 4070+ have nothing to do with reality, as shown by tests of top Apple chips, which are not capable, with a real memory bandwidth of 120 GB / s, of competing on equal terms, even with the mobile 4050, with Max chip options.
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How stupid are those who reserve registered accounts with NikoB, in fruitless attempts to remove me from the forum.

[heffeque]

How stupid are those who reserve registered accounts with NikoB, in fruitless attempts to remove me from the forum.

How self-important can one be?
If the owners of the web page don't want you here, why insist on coming back?
I'd recommend you take your wisdom somewhere else where you are wanted.
Sounds logical and what a normal human being would do, right?

[Gibi]

Apple chips, which are not capable, with a real memory bandwidth of 120 GB / s

Another bullshit analytics. Even quick googling
www.anandtech.com/show/17024/apple-m1-max-performance-review/2
shows you can achieve 243GB/s even on m1max and authors say that problem is not "fake" bandwidth but they couldn't come up with task that can achieve the full bandwidth, aka stress CPU+GPU+NPU to full extent.