Upcoming AMD Ryzen with 8 Zen 5 cores and 16 Zen 4D cores to potentially thwart Intel's hybrid advances, Zen 4D to offer massive multi-core gains at Zen 3 IPC levels

[Redaktion]

AMD could be looking to introduce a Zen 4D contemporary to Zen 4 Raphael that would focus more on multi-core performance even if it means reduced single-core gains. Zen 4D is slated to launch with Bergamo EPYC parts but are likely to be available on the desktop or even consoles such as the PS5 Pro. In 2023, AMD is expected to launch a hybrid solution with up to eight Zen 5 performance cores and 16 Zen 4D efficiency cores on the AM5 platform.

https://www.notebookcheck.net/Upcoming-AMD-Ryzen-with-8-Zen-5-cores-and-16-Zen-4D-cores-to-potentially-thwart-Intel-s-hybrid-advances-Zen-4D-to-offer-massive-multi-core-gains-at-Zen-3-IPC-levels.577566.0.html

[8&8]

I want to be sincere; from when AMD in their presentations put photos, diagrams about Zen4? When came Zen arch, was never mentioned Zen4. There was a step from Zen3 to Zen5.

The only things that can do is moving from Zen3+/3D to Zen5 MCM including a decent iGPU.

And invest time/energy/money/minds to scaling vector tech and new semiconductors.

[Patrick123]

Zen4 is not even in the market yet. Hold on with Zen5 speculation

[Rob Stan]

Not sure where you peeps got the "at Zen 3 IPC levels" bit that sounds completely made up by this article and isn't supported by any reasonable speculation either. The leak simply states Zen4D is a variation on Zen4 architecture, with clocks that  focus on best clock/power ratios, slightly less cache and that it'll likely keep SMT (unlike Intel's small cores), as speculation that IT MIGHT not have AVX512, like regular Zen4 has (tho this might create problems like ADL has IMHO).

It says nothing about IPC and the only thing that can be speculated is that cache-sensitive workloads may contribute to it having slightly less IPC than regular Zen4 cores. But considering these supposedly comes a bit after Zen4/Raphael/Genoa, we don't really know how Zen4D is similar to regular Zen4 cores, maybe they're more aching to a Zen4+ design for all we know, maybe not.

Maybe don't add your own stuff that isn't in the supposed leak itself next time.

[Hang Lai]

Intel' is making Intel'4 chips now, no matter what AMD will have later, it will be at least one gen behind, AMD will really in hot water when Intel' catch up with TSMC in 2023 in 3nm. I am sorry

[riklaunim]

Intel' is making Intel'4 chips now, no matter what AMD will have later, it will be at least one gen behind, AMD will really in hot water when Intel' catch up with TSMC in 2023 in 3nm. I am sorry

Competition is good. Monopoly is not. Right now Intel used 10nm to make a high end part. This is somewhat better or equal to TSMC 7nm. AMD is moving to 5nm for Zen 4 so the competition should easily still be there, no need for "it's over" doom talk. Intel 7nm that would be it equivalent also will need some time to enter actual use - and the lower both Intel or TSMC goes it only gets harder.

[Anonymousgg]

Not sure where you peeps got the "at Zen 3 IPC levels" bit that sounds completely made up by this article and isn't supported by any reasonable speculation either. The leak simply states Zen4D is a variation on Zen4 architecture, with clocks that  focus on best clock/power ratios, slightly less cache and that it'll likely keep SMT (unlike Intel's small cores), as speculation that IT MIGHT not have AVX512, like regular Zen4 has (tho this might create problems like ADL has IMHO).

It says nothing about IPC and the only thing that can be speculated is that cache-sensitive workloads may contribute to it having slightly less IPC than regular Zen4 cores. But considering these supposedly comes a bit after Zen4/Raphael/Genoa, we don't really know how Zen4D is similar to regular Zen4 cores, maybe they're more aching to a Zen4+ design for all we know, maybe not.

MLID talks about IPC at 17:13 in the video. Notebookcheck's characterization of "Zen 3 or Zen 3 with Vcache IPC levels" is consistent with the leak in my opinion. The worst case scenario should have Zen 4D at around Zen 3 IPC, best case would be more like Zen 3 w/ 3D VCache, which I guess shouldn't be called Zen 3D anymore (but also not Zen 3+ depending on what changes Rembrandt has). Clocks would be lower in any case.

Whatever it is, you'll still end up with 8 fast Zen 5 cores, and the 16 Zen 4D cores will have hyperthreading for a total of 48 threads. It should have better multithreaded performance than 16 Zen 5 cores would.

AVX-512 should be dropped on Zen 4D if it is taking up a lot of die space in Zen 4 cores. While having it turned off on some cores but not others could be a problem, it should be noted from AnandTech's coverage that Intel was preparing to ship Alder Lake with AVX-512 enabled:

Based on a variety of conversations with individuals I won't name, it appears that the plan to have AVX-512 in Alder Lake was there from the beginning. It was working on early silicon, even as far as ES1/ES2 silicon, and was enabled in the firmware. Then for whatever reason, someone decided to remove that support from Intel's Plan of Record (POR, the features list of the product).

By removing it from the POR, this means that the feature did not have to be validated for retail, which partly speeds up the binning and testing/validation process. As far as I understand it, the engineers working on the feature were livid.

AMD has another 2 years to make mixed AVX-512 work with Windows and Linux. Maybe Raptor Lake will prove it can work.