First complete PCIe 7.0 IP solution presented by Synonpsis coming to market in 2025 for HPCs and AI supercomputers

[Redaktion]

A 128 Gb/s PCIe 7.0 lane with electrical-optical-electrical technology will be demonstrated at this year's PCI-SIG Developers Conference in the coming days. Synopsys estimates that the complete PCIe 7.0 IP with controller, IDE security model, PHY and additional verification IP, as well as the full slot integrating X16 lanes capable of 512 GB/s bidirectional transfers should be available in 2025.

https://www.notebookcheck.net/First-complete-PCIe-7-0-IP-solution-presented-by-Synonpsis-coming-to-market-in-2025-for-HPCs-and-AI-supercomputers.847206.0.html

[Alexey]

Please fix the title: it is "Synopsys", not "Synopsis".

[Bogdan Solca]

Please fix the title: it is "Synopsys", not "Synopsis".

Fixed now.

[NikoB]

As funny as it may seem, stupid (or greedy) laptop manufacturers still leave at least 16 pci-e 5.0 lanes hanging in the air in Zen4 (where there are 28 lanes!). If they ignore free pci-e 5.0 lanes in laptops, further increases in bandwidth pci-e bus are pointless for laptops. And it is especially pointless if the RAM bandwidth of laptops is not increased at least 5 times immediately to real (in real tests) 250-300GB/s for typical laptop. And at 10 times for top-end laptops with HBM3e 512-1024 bit data bus..

This is a site about laptops, right?