China finalizes work on proprietary "Loong Arch" CPU instruction set that does not conflict with foreign CPU patents

[Redaktion]

Loongson is the company behind the development of the "Loong Arch" instruction set - China's first domestic CPU instruction set. According to third-party IP evaluators, Loong Arch is completely original and does not conflict with other foreign IPs. It is still compatible with other mainstream architectures like x86, RISC-V and MIPS.

https://www.notebookcheck.net/China-finalizes-work-on-proprietary-Loong-Arch-CPU-instruction-set-that-does-not-conflict-with-foreign-CPU-patents.532725.0.html

[kek]

"Loongson claims that the new instruction set is completely original and allows Chinese CPU makers to produce processors without the need to get special licenses from foreign companies."

Doubt (X)

I wonder who is that "third party IP" company lol.

[druiser]

MIPS is already China property. They don't need to buy it
Loongson CPU were already more than MIPS64

Now they launch their own ISA, something expected. China invests a lot in a semi-conductors.
LoogArch will be open source and given to other Chinese compagnies

ps : They already designed Shenwei architecture and it was not based on Dec Alpha. 
So, they have already a huge knowledge. They are  first or second in number of patents and are already in front when it is about IA related patent.

[vertigo]

So they've designed a (supposedly) completely unique instruction set that doesn't use any preexisting architectural designs, which to me seems like it will be less efficient, i.e. slower, due both to having to specifically avoid what may be an optimal method and having to take code designed for other instruction sets and translate it first before processing it. And regardless of how fast that translation is, it's still an extra step. But then it may be more efficient due to possibly designing more optimal methods in the process, ditching outdated parts, and writing code that can be processed directly without translation. Is that an accurate assessment?

[ts]

it will be less efficient, i.e. slower, due both to having to specifically avoid what may be an optimal method and having to take code designed for other instruction sets and translate it first before processing it

Not necessarily.

First, they do not need to translate instructions if they intend to develop software stack (compiler's backend) and extract maximum performance by executing native code.

Second, avoiding patent infridgement doesn't mean avoiding optimal method if it is connected with interpretation of instruction codes - I wouldn't be surprised if some or most of x86 patents are related to instruction codes (like extending into 64 bit with x86-64 from plain x86) and don't say anything about hardware implementation of instruction routines (which are covered by different patents)

Third, ISA created from scratch doesn't mean it must be less efficient than existing one. For example, decoding variable length instructions without clear boundaries in x86 case is not easy and it is said to be one of the reasons why x86 decoders need substantial amount of power and current CPUs are limited in instruction fetch bandwidth. Being still able to execute 30-years code may sound attractive, but it is quite a high burden for instruction decoder.

[vertigo]

it will be less efficient, i.e. slower, due both to having to specifically avoid what may be an optimal method and having to take code designed for other instruction sets and translate it first before processing it

Not necessarily.

First, they do not need to translate instructions if they intend to develop software stack (compiler's backend) and extract maximum performance by executing native code.

I may be misunderstanding, but it seems you're actually confirming my point. At some point, it will require a translation, since code that is written for one instruction set needs to run on another. Granted, this may have a very small impact on performance, but it's still one extra step and therefore at least a bit slower, even if negligible. Unless code is written specifically for the new instruction set.

Third, ISA created from scratch doesn't mean it must be less efficient than existing one. For example, decoding variable length instructions without clear boundaries in x86 case is not easy and it is said to be one of the reasons why x86 decoders need substantial amount of power and current CPUs are limited in instruction fetch bandwidth. Being still able to execute 30-years code may sound attractive, but it is quite a high burden for instruction decoder.

Not saying it must be less efficient, just that it might be since they may have been forced to use less than ideal methods in order to avoid infringement. Then again, it's also possible that they may have developed even better methods, since they weren't beholden to maintaining compatibility. And as I and the article mentioned, they would have gained some efficiency from being able to abandon old, unnecessary instructions, which is what you're referring to in regard to this. So my point was that there are likely elements involved that reduce the efficiency, ones that increase it, and ones that could go either way, so we won't know the total net improvement or reduction in performance until there are production samples to test, but it just seemed like they have a lot of things working against them.