No matter how many "cheats" they introduce in the form of increased L1/L2/L3/L4 cache - it's all useless. Need RAM with a bandwidth of over 300GB/s. Many cores simply choke on a slow memory bus.

Servers have long been equipped with HBM memory with a bandwidth of 1TB/s+.

For igpu to work quickly - they also need a RAM bandwidth (which is shared with the rest of the hardware/OS and software) of 500GB/s+.

Therefore, even the 256-bit Zen5 Halo Point controller (whose efficiency is highly questionable, against the backdrop of Apple's disgrace with its 512-bit Max versions, as real tests have shown - the efficiency was below 35%), which we have all been waiting for a long time with sadness, in fact, has long been morally obsolete in terms of "overclocking" cores and igpu, not to mention the current shameful solutions from 50 up to 100GB/s (Zen5 Strix Point/Lunar Lake, and only in versions with soldered memory) on average for r/w/c operations.

Let me also remind you that, unlike SSD, the latency of access to RAM does NOT fall, but GROWS over the years - which only exacerbates the catastrophe with access speed and RAM bandwidth.

Even C2D cores can be significantly "overclocked" if they were given RAM at 100GB/s+, even this architecture can easily handle this data flow, as can be seen from the C2D L1 cache tests.

x86 hardware has become completely unbalanced in terms of RAM bandwidth over the years.

NikoB.

cant wait for the day we have 1gb cache