You say it differs from GaaFET. How exactly? As far as I know, nanosheet transistors are gate-all-around. The concept of a gate-all-around transistor appeared around 30 years ago if I remember my computer history correctly. About 15 years ago, someone came up with the idea of using thin sheets instead of thin wires. Because the wires were just too thin. So, how exactly do they differ? I think everybody is going to use sheets.

Also, the numbers confuse me a bit. IIRC, when they started working with nanosheets on a 5 nm process, they promised something very similar - 40 % more performance and 75 % less energy use compared to a 7 nm process. Which is impressive. It's not impressive if you make that claim for a 2 nm process compared to a 7 nm process. That's three generations (7, 5, 3, 2).

A side note, 75 % less energy used is not the same as 75 % higher efficiency. It's 300 % higher efficiency. Or four times the efficiency. One is inverse of the other. If one is 1/4 (100-75), the other is 4 (100+300). Elementary mathematics.

It's sad to hear so many silly mistakes (or perhaps imprecise and misleading formulations) in a video from IBM. It's like they didn't show it to any of their engineers. For example, calling transistor a type of semiconductor. Sure. :D A child with primary education should know what a semiconductor is. That's elementary physics. Blurring that definition serves nothing except promotion of sloppiness and dilettantism. Call me old-school if you want.