If this is true, I'm going to finally retire my Ryzen 5 1600, this will be more than a worthy upgrade, especially for game streaming, and video editing. Either way 4000 is supporting b450, so I'm upgrading anyhow, now the distinction between 3000 and 4000 will be even bigger. Ryzen 5 4600 will more than most users demands.

Quote from: jeremy on May 28, 2020, 19:16:04
Like Zen+, it doesn't have to involve floorplan changes. Simply shrinking certain transistors in place can be enough to make a difference. Sure, timing and routing will still require more work, but smaller IP blocks, along with fab provided IP (usually PHYs and SRAM) can see improvements. That's what 5nm really means for TSMC (vs 7nm; similar to "12nm" vs "16nm" at TSMC).

Also, iirc, part of 5nm at TSMC was reducing the number of steps in fabrication, allowing for faster turnaround and greater wafer volume - all beneficial additions from 5nm over just using 7nm (dunno about EUV variants of the 7nm node).

Except that AMD stated repeatedly that Zen 3 will come with a change in architecture.
So its not a simple minor progression like Zen1 to Zen + was.
Even Zen 2 was not considered a full architecture change... but more along the lines of fully maxing out Zen 1 and + as it was originally envisioned.

However, I'm skeptical that Zen 3 will be done on 5nm.
AMD's own roadmaps state that Zen 3 is on 7nm and 5nm was slated for next year (2021) along with Zen 4.

On the other hand, 5nm was ramping up and by mid-late 2019, it already achieved over 50% yields (better than what 7nm achieved).

As for whether AMD can simply 'port' Zen 3 to 5nm on such short notice.... not sure... we're talking about a design which was finalized a year in advance... however, its possible they designed Zen 3 so that it can be more easily 'ported' to a node shrink.

I mean, AMD did manage to create Vega VII that way...

But, this would radically affect the design seeing how 5nm opens up options for increase in number of cores, etc.
Unless they decide to stick with Zen 3 design as is and just port it to 5nm...

I guess we'll see, but I remain skeptical that Zen 3 will be done on 5nm

STAHP, HE'S ALREADY DEAD

Interesting, so the ban on Huawei can hit hard on Intel then.

Like Zen+, it doesn't have to involve floorplan changes. Simply shrinking certain transistors in place can be enough to make a difference. Sure, timing and routing will still require more work, but smaller IP blocks, along with fab provided IP (usually PHYs and SRAM) can see improvements. That's what 5nm really means for TSMC (vs 7nm; similar to "12nm" vs "16nm" at TSMC).

Also, iirc, part of 5nm at TSMC was reducing the number of steps in fabrication, allowing for faster turnaround and greater wafer volume - all beneficial additions from 5nm over just using 7nm (dunno about EUV variants of the 7nm node).