Quote from: _MT_ on March 05, 2020, 15:03:00

Quote from: Valantar on March 04, 2020, 09:41:51
Which obviously makes something like this impossible to implement for a semi-custom console APU - they would need to discard >90% of chips! That would not only be idiotic, but would drive console prices through the roof (with at least a 10x price increase for the SoC).
...
Zen2 on 7nm has its efficiency sweet spot around the ~3.2-3.5GHz mark

Not entirely true. The cost of a chip is not just the cost of manufacture. And even in manufacture, I'm not that familiar with integrated circuit manufacture, but in general, there are often significant one-time expenses. Also, if you take a modular approach (multiple chiplets), the situation improves (you're discarding fewer cores/ smaller piece of silicon). Yes, a 10 % yield in a chip for a high volume consumer product is not going to be acceptable.

That's pretty high. A few years ago, there was a paper where they determined 200 MHz to 1.6 GHz as a "sweet window" with efficiency being pretty flat in this range. I'm not sure what they studied, but it was a phone SoC, I believe. In general, as density goes up (nodes get finer), leakage current becomes a bigger and bigger problem. The cost of simply having the core "switched on" is getting relatively larger which is what's driving the bottom end of the range. At the high end, voltage is the killer. The higher the frequency, the higher the required voltage for stable operation. And power rises with the square of voltage. A 10 % increase in voltage is a 21 % increase in power. I wouldn't really expect the sweet spot to be significantly above 2 GHz going by the specifications of Epyc Rome.

You can't just go and compare clock/voltage sweet spots across different nodes - or even different architectures on the same node - so that comparison is entirely invalid. Also, PC chips generally use high performance libraries for their designs rather than the high density and/or high efficiency ones mobile SoCs use, which has dramatic effects on clock scaling and where the efficiency curve starts rising dramatically. Mobile SoCs are far more efficient at low clocks, but can't clock even close to as high as PC chips, with efficiency typically plummeting somewhere between 2 and 3 GHz with a hard stop close after that. On the other hand the efficiency curves of desktop chips tend to be relatively flat for a long time, meaning they don't get particularly efficient at low clocks (hence why tiny ARM cores have better battery life), but scale quite high before becoming inefficient, and still keep going for a while after that before becoming unstable. And as I said, the per-core power draw of a Zen2 core in a Threadripper 3990X (which, barring binning differences, is the same as any other Zen2 core) is just ~3W at 3.45GHz, while a single core boosting to 4.5 can consume around 6x that number if not more. In other words, that's pretty much the sweet spot for that chip on that node. Subtracting a few hundred MHz for binning and for margin to allow as many chips as possible to pass QC and you have a 3-3.2GHz very efficient console CPU.

As for manufacturing, it's highly unlikely that a console will use chiplets.  While this would bring down die sizes and lower prices that way, packaging would be more expensive, and you'd need a third I/O die as both CPU and GPU need equal access to the unified memory of the system, complicating things quite a bit on the manufacturing side. Of course this is guesswork, but a monolithic die is still by far the most likely. You are of course right that R&D is a very significant part of the cost of the chip though, so I should have said a 10x increase in the manufacturing cost of the SoC.

Quote from: Valantar on March 04, 2020, 09:41:51
Which obviously makes something like this impossible to implement for a semi-custom console APU - they would need to discard >90% of chips! That would not only be idiotic, but would drive console prices through the roof (with at least a 10x price increase for the SoC).
...
Zen2 on 7nm has its efficiency sweet spot around the ~3.2-3.5GHz mark

Not entirely true. The cost of a chip is not just the cost of manufacture. And even in manufacture, I'm not that familiar with integrated circuit manufacture, but in general, there are often significant one-time expenses. Also, if you take a modular approach (multiple chiplets), the situation improves (you're discarding fewer cores/ smaller piece of silicon). Yes, a 10 % yield in a chip for a high volume consumer product is not going to be acceptable.

That's pretty high. A few years ago, there was a paper where they determined 200 MHz to 1.6 GHz as a "sweet window" with efficiency being pretty flat in this range. I'm not sure what they studied, but it was a phone SoC, I believe. In general, as density goes up (nodes get finer), leakage current becomes a bigger and bigger problem. The cost of simply having the core "switched on" is getting relatively larger which is what's driving the bottom end of the range. At the high end, voltage is the killer. The higher the frequency, the higher the required voltage for stable operation. And power rises with the square of voltage. A 10 % increase in voltage is a 21 % increase in power. I wouldn't really expect the sweet spot to be significantly above 2 GHz going by the specifications of Epyc Rome.

Quote from: Thomas Serruques on March 03, 2020, 22:18:47
Bullshit, the 4800H or 4900H are very capable 8/16 CPUs and their TDP is 35W.. So there is enough room for a capable Zen2 8/16 CPU between 3,2 and 4GHz boost clock. The CPU of next gen consoles will be much better than a 7nm 1600X.

Mobile chip TDPs are normally rated for base clocks, which are 3.0 GHz (4600H) and 2.9GHz (4800H) respectively for those parts. They might boost higher depending on cooling and chip-specific power levels, but they are not guaranteed to exceed base clock at TDP levels of power draw. Also their TDPs are 45W, not 35W - the 35W parts are the HS parts, which are a special high-efficiency bin of the same silicon, and likely a relatively low percentage of dies produced are capable of running at power levels this low - that's how the silicon lottery works. It's very likely less than 10% of all Renoir silicon is capable of running those clocks at 35W. Which obviously makes something like this impossible to implement for a semi-custom console APU - they would need to discard >90% of chips! That would not only be idiotic, but would drive console prices through the roof (with at least a 10x price increase for the SoC).

Zen2 on 7nm has its efficiency sweet spot around the ~3.2-3.5GHz mark (AnandTech measured per-core draw for the 64-core 3990X at ~3W each at 3.45GHz) but you also need to take Infinity Fabric power draw and other parts (memory controller etc.) into the equation here, which will be rather significant at these power levels and the sheer size of the memory bus for a console like this. But depending on yields it's not unlikely that we can see a 8c16t Zen2 at ~3.2GHz for these consoles (the higher you push the higher the reject rate for chips that fail to meet power/clock speed targets, so for consoles clocks are always conservative).

Or writing headlines that say something different than the articles. Having Ryzen 5 1600 level of performance is a different thing compared to having a Ryzen 5 1600 chiplet manufactured using 7 nm process. If you can't see the difference, you shouldn't be writing. Especially since your own article mentions they're going to use Zen 2. The "older 1600" is not Zen 2.

@Thomas Serruques: So, you're disputing the leaked specification on which the estimate is based on.

Bullshit, the 4800H or 4900H are very capable 8/16 CPUs and their TDP is 35W.. So there is enough room for a capable Zen2 8/16 CPU between 3,2 and 4GHz boost clock. The CPU of next gen consoles will be much better than a 7nm 1600X.

i'm agree with you brother

Can you please stop paraphrasing your sources into saying things they aren't saying?

Point one:
A 7nm Zen2 CPU clocked low and thus at equivalent performance of a Ryzen 5 1600 is not at all a "7 nm version of the older Ryzen 5 1600 processor". And the Zen2 architecture is confirmed by both console makers. So that statement is factually false. For it to be what you say it would need to have the Zen 1 architecture at the very least, and also really would need to run at the same clock speeds (and be a discrete chip, really, not an APU).

Point two:
A 9.78 TFlop RDNA2 GPU in a console APU is not at all a "custom-made Radeon RX 5700 XT". Firstly, the 5700 XT is RDNA (1), not RDNA 2. Secondly, equivalent performance - or even equivalent design, with the same number of CUs etc. - does not make them the same part. One is an APU design, the other is a standalone GPU. Just because the use similar building blocks in a similarly sized layout does not make them the same. You can say they are like each other, but again, saying they are the same is factually false.

If you are trying to make a point about similarities between the two you need to be precise in your use of language. This is terrible, sloppy journalism and not worthy of a quality site like notebookcheck.