Initially scheduled for mid-2019, risk production for the upcoming 5 nm manufacturing process was already initiated at the end of March. TSMC also finalized the 5 nm design infrastructure and it is currently testing this process through multiple silicon test vehicles. Improvements over the current 7 nm process include 1.8X increased logic density and a 15% performance boost.
https://www.notebookcheck.net/TSMC-initiates-risk-production-for-its-5-nm-node-reveals-performance-details.415837.0.html