AMD Zen 5 architecture leak reveals 22-30% IPC gain as well as a much bigger L1, unified L2, and a possible shared L4 cache for APUs

[Redaktion]

Paul from RedGamingTech has revealed updated information regarding 2024's AMD Zen 5 CPU architecture. According to the leaker, Zen 5 could have a double-digit IPC uplift, significantly bigger L1 cache, and 8 cores per CCX. Most of these specs seem to confirm what Paul has mentioned previously.

https://www.notebookcheck.net/AMD-Zen-5-architecture-leak-reveals-22-30-IPC-gain-as-well-as-a-much-bigger-L1-unified-L2-and-a-possible-shared-L4-cache-for-APUs.691715.0.html

[Räuber Hotz]

At this point in time, it's ridiculous and redundant to talk about Zen5/APU gains. We don't even have decent Zen4 APUs out yet. First of all we need gains in Zen4/APUs availability, especially for mobile and desktop Zen4-7000G processors.

[88&88]

At this point in time, it's ridiculous and redundant to talk about Zen5/APU gains. We don't even have decent Zen4 APUs out yet. First of all we need gains in Zen4/APUs availability, especially for mobile and desktop Zen4-7000G processors.

to not talk that -Zen5 apu will be again dual channel ddr5 6400
                 -not HBM2 memory to replace ddr5 bottleneck bandwith like in MI300
                 -still 12CU's iGPU instead of (at least) 20CU.

[88&88]

-PCIe5 ?
- 8cores how 4C Zen5 with 4c Zen4d?
-bigger cache or 3D cache?
-RDNA4 or RDNA3+?
-with how many CUs? >12Cu I hope

780m of 7940Hs is similar to GTX780Ti ~ GTX1050Ti

c'mon amd a little MI300 at 3nm

[Räuber Hotz]

-with how many CUs? >12Cu I hope

I guess that will happen. There has already been a rumor that it will have up to 24 CUs. While 24 CUs were also rumored for the 780m (and didn't happen), it will most likely happen for the 880m.

[NikoB]

All these improvements are already completely useless, as well as increasing the L3 cache above 100MB - because x86 need to increase the memory bus width to 512 bits, like Apple has, where the memory speed (according to their declarations, not verified anywhere, I have not seen tests) in M2 Max has already outperformed the Raptor Lake memory controller by more than 4 times - with 400GByte/s theoretical limit.

Intel/AMD and the entire x86 camp turned out to be outsiders in this regard at once...

[Räuber Hotz]

All these improvements are already completely useless, as well as increasing the L3 cache above 100MB - because x86 need to increase the memory bus width to 512 bits, like Apple has,

Intel/AMD and the entire x86 camp turned out to be outsiders in this regard at once...

You're probably right, that this would improve performance significantly.

However... I was looking for benchmarks Apple M2 vs AMD Radeon 680m - and in the few gaming benchmarks I found, the 680m still clearly comes out on top.

[Dwarfcow]

All these improvements are already completely useless, as well as increasing the L3 cache above 100MB - because x86 need to increase the memory bus width to 512 bits, like Apple has, where the memory speed (according to their declarations, not verified anywhere, I have not seen tests) in M2 Max has already outperformed the Raptor Lake memory controller by more than 4 times - with 400GByte/s theoretical limit.

Intel/AMD and the entire x86 camp turned out to be outsiders in this regard at once...

That kind of bandwidth is important for video/graphical information, which is what apple is using their 400GB/sec for  but you're talking about desktop pc's we have over 1000GB/sec for our dedicated graphics systems (ala 3090/4090 GPUs) at 384bit bus.

[Anonymousgg]

At this point in time, it's ridiculous and redundant to talk about Zen5/APU gains. We don't even have decent Zen4 APUs out yet. First of all we need gains in Zen4/APUs availability, especially for mobile and desktop Zen4-7000G processors.

I'd rather talk about Strix Point than Phoenix.

The only thing interesting in Phoenix is the XDNA AI accelerator. Strix might bring 12-16 cores too.

[Truther]

AMD is actually going huge things every year, objective performance gains where it matters every time

[NikoB]

That kind of bandwidth is important for video/graphical information, which is what apple is using their 400GB/sec for  but you're talking about desktop pc's we have over 1000GB/sec for our dedicated graphics systems (ala 3090/4090 GPUs) at 384bit bus.

The trick is that there the processor Apple normally works with the same high-speed memory. And on x86, a bunch of laptops with fast processors are choking on much slower memory. Which is absurd and ridiculous and shameful for x86 manufacturers. And there are not even discrete cards.

Otherwise, the shameful Intel/AMD would not increase the L3 cache many times over in the latest models. Their engineers know very well why I make fun of them.

[TiTi]

32 cores and hybrid architecture? According to previous leaks (MLID?), this will probably be two CCD of 8 Zen 5 and one CCD of 16 Zen 4D (from Bergamo)

[TiTi]

-with how many CUs? >12Cu I hope

I guess that will happen. There has already been a rumor that it will have up to 24 CUs. While 24 CUs were also rumored for the 780m (and didn't happen), it will most likely happen for the 880m.

Not. RDNA 3 has doubled the number of Stream Processor per CU. 12 CU RDNA 2 = 768 SP and 12 CU RDNA 3 = 1536 SP (in short).
The leaker has misinterpreted his leaks regarding Phoenix. He heard 1536 SPs and thought 24 CU.

[Anonymousgg]

32 cores and hybrid architecture? According to previous leaks (MLID?), this will probably be two CCD of 8 Zen 5 and one CCD of 16 Zen 4D (from Bergamo)

I don't remember seeing that as a leak (8+8+16 specifically), but I've seen that speculation.

If AMD is "generous" enough to include a 16-core Zen 4C on even the low-end Granite Ridge (Zen 5 desktop), then it could eliminate Intel's multi-threaded advantage immediately. For example, a 6-core 7600X could become an 18-core (6+12). It's not that outlandish since the 13600K has 14 cores.

7950X3D and 7900X3D are almost like a test run of AMD hybrid/heterogeneous. Since one of the key differences of Zen 5 + Zen 4C would be the asymmetric cache amounts.